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(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
Memory
Logic Diagram
FEATURES:
* 8K x 16-bit dual port RAM - Stand Alone - Master Slave * RAD-PAK(R) radiation-hardened against natural space radiation * Total dose hardness: - > 100 krad (Si), depending upon space mission * Excellent Single Event Effects: -SELTH LET = >100 MeV/mg/cm2 -SEUTH LET = 7 MeV/mg/cm2 * Package: -84 Pin RAD-PAK(R) quad flat pack * Separate upper byte and lower byte control for multiplexed bus compatibility * High speed access time: 35/45 ns * Expandable to 32 bits or more using master/slave select when cascading * High speed CMOS technology -TTL compatible, single 5V power supply -Interrupt flag for port-to-port communication -On chip port arbitration logic -Asynchronous operation from either port
DESCRIPTION:
Maxwell Technologies' 7025E Dual Port RAM High Speed CMOS(R) microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. The 7025E is designed to be used as a stand-alone 128k-bit Dual Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32bit or more word systems. This design results in full-speed, error-free operation without the need for additional discrete logic. The 7025E provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CS permits the on-chip circuitry of each port to enter a very low standby power mode. Maxwell Technologies' patented RAD-PAK(R) packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S.
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
TABLE 1. 7025E PINOUT DESCRIPTION
NAMES Chip Select Read/Write Select Output Select Address Data Input/Output Semaphore Select Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag M/S VCC GND LEFT PORT CSL R/WL OSL AOL-A12L I/OOL-I/O15L SEML UBL LBL INTL BUSYL RIGHT PORT CSR R/WR OSR AOR-A12R I/OOR-I/O15R SEMR UBR LBR INTR BUSYR Master or Slave Select Power Ground
7025E
Memory
TABLE 2. 7025E ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (Relative to VSS) Operating Temperature Range Input or Output Voltage Applied Storage Temperature Range SYMBOL VCC TA -TSTG MIN -0.3 -55 GND -0.3V -65 MAX 7.0 125 VCC+ 0.3 150 UNITS V
C
V
C
TABLE 3. DELTA LIMITS
PARAMETER ICCOP ICCOP1 ICCSB ICCSB1 VARIATION 10% AS STATED I TABLE 6 10% AS STATED I TABLE 6 10% AS STATED I TABLE 6 10% AS STATED I TABLE 6
TABLE 4. 7025E RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage Positive Input Voltage SYMBOL VCC VIL VIH
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MIN 4.5 -0.5 2.2
MAX 5.5 0.8 6.0
UNITS V V
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
TABLE 4. 7025E RECOMMENDED OPERATING CONDITIONS
PARAMETER Thermal Impedance Operating Temperature Range SYMBOL MIN --55 MAX 1.02 125
7025E
UNITS C/W
C
JC
TA
TABLE 5. 7025E CAPACITANCE
PARAMETER Input Capacitance: VIN = 0V1 Output Capacitance: VOUT = 1. Guaranteed by design. 0V1 SYMBOL CIN COUT MIN --MAX 5 7 UNITS pF pF
TABLE 6. 7025E DC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = -55 TO 125 C UNLESS OTHERWISE) PARAMETER Input Leakage Current 1 Output Leakage Current
2
Memory
SYMBOL ILI ILO ICCSB
SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3
MIN -----
MAX 10 10 50 50
UNITS A A mA
Standby Supply Current, Both ports TTL level inputs -35 -45 Standby Supply Current, Both ports CMOS level inputs -35 -45 Operating Supply Current, Both ports Active -35 -45 Operating Supply Current, One Port Active, One Port Standby -35 -45 Input Low Voltage3 Input High Voltage Output Low Voltage 4 Output High Voltage 1. VCC = 5.5V, VIN = GND to VCC, CS = VIH, VOUT = 0 to VCC. 2. Vcc=5.5V; Vout = GND to Vcc 3. VIH max = VCC + 0.3V, VIL min = -0.3V or -1V pulse width 50 ns 4. VCC min, IOL = 4 mA, IOH = -4 mA.
ICCSB1
1, 2, 3 --1, 2, 3 --1, 2, 3 --1, 2, 3 1, 2, 3 -2.2 -2.4 190 180 0.8 -0.4 -320 280 5 5
mA
ICCOP
mA
ICCOP1
mA
VIL VIH VOL VOH
V V
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
TABLE 7. 7025E AC ELECTRICAL CHARACTERISTICS FOR READ CYCLE
(VCC = 5V 10%, VSS = 0V, TA = -55 TO 125 C) PARAMETER Read Cycle Time -35 -45 Address Access Time -35 -45 Chip Select Access Time 1 -35 -45 Byte Select Access Time 1 -35 -45 Output Select to Output Valid -35 -45 Output Low Z Time 2,3 -35 -45 Output High Z Time 2,3 -35 -45 Chip Enable to Power Up Time 2 Chip Disable to Power Up Time 2 Semaphore Flag Update Pulse (OE or SEM) SYMBOL tRC SUBGROUPS 9, 10, 11 35 45 9, 10, 11 --9, 10, 11 --9, 10, 11 --9, 10, 11 --9, 10, 11 3 3 9, 10, 11 --9, 10, 11 9, 10, 11 9, 10, 11 0 -15 20 20 -50 ---20 25 35 45 35 45 35 45 --MIN
7025E
MAX
UNIT ns
tAA
ns
tACS
ns
tABE
ns
tAOE
ns
Memory
tLZ
ns
tHZ
ns ns ns ns
tPU tPD tSOP
1. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIN and SEM = VIL. Either condition must be valid for the entire tEW time. 2. Guaranteed by design. 3. Transition is measured 500 mV from low or high impedance voltage with load.
TABLE 8. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE CYCLE
(VCC = 5V 10%, VSS = 0V, TA = -55 TO 125 C) PARAMETER Write Cycle Time -35 -45 Address Valid to End of Write -35 -45
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SYMBOL tWC
SUBGROUPS 9, 10, 11
MIN 35 45
MAX ---
UNIT ns
tAW
9, 10, 11 30 40 ---
ns
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
TABLE 8. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE CYCLE
(VCC = 5V 10%, VSS = 0V, TA = -55 TO 125 C) PARAMETER Chip Select to End of Write 1 -35 -45 Address Setup Time -35 -45 Write Pulse Width -35 -45 Write Recovery Time -35 -45 Data Valid to End of Write -35 -45 Output High Z Time 2,3 -35 -45 Data Hold Time -35 -45 Write Select to Output in High Z 2,3 -35 -45 Output Active from End of Write -35 -45 SEM Flag Write to Read Time -35 -45 SEM Flag Contention Window -35 -45
2,3,4
7025E
SUBGROUPS 9, 10, 11 30 40 9, 10, 11 0 0 9, 10, 11 30 35 9, 10, 11 0 0 9, 10, 11 25 25 9, 10, 11 --9, 10, 11 0 0 9, 10, 11 --9, 10, 11 0 0 10 10 10 10 --ns --ns --20 20 ns --ns 20 20 ns --ns --ns --ns --ns --ns MIN MAX UNIT ns
SYMBOL tSW
tAS
tWP
tWR
tDW
Memory
tHZ
tDH
tWZ
tOW
tSWRD
tSPS
1. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIN and SEM = VIL. Either condition must be valid for the entire tEW time. 2. Guaranteed by design. 3. Transition is measured 500 mV from low or high impedance voltage with load. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tDW.
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 9. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE MASTER/SLAVE CONFIGURATION
(VCC = 5V 10%, VSS = 0V, TA = -55 TO 125 C) PARAMETER For Master Only BUSY Access Time to Address Match -35 -45 BUSY Disable Time to Address Not Matched -35 -45 BUSY Access Time to Chip Select Low -35 -45 BUSY Disable Time to Chip Select High -35 -45 Write Pulse to Data Delay 1 -35 -45 Write Data Valid to Read Data Delay 1 -35 -45 Arbitration Priority Setup Time 2 -35 -45 BUSY Disable to Valid Data -35 -45 For Slave Only Write to BUSY Input 4 Write Hold after BUSY 5 Write Pulse to Data Delay 1 -35 -45 Write Data Valid to Read Data Delay 1 -35 -45 tWB tWH tWDD 0 25 ------60 70 ns 45 55 ns ns ns tBAA ns ------------5 5 --35 35 ns 30 30 ns 30 30 ns 25 25 ns 60 70 ns 45 55 ns --ns
3 3
SYMBOL
MIN
MAX
UNIT
tBDA
tBAC
tBDC
Memory
tWDD
tDDD
tAPS
tBDD
tDDD
1. Port to port timing delay through RAM cells from writing port to reading port. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tWD (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention.
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All data sheets are subject to change without notice
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 10. 7025E AC PARAMETERS FOR INTERRUPT TIMING
(VCC = 5V 10%, TA = -55 TO 125 C, f = 1 MHZ) PARAMETER Address Setup Time Write Recovery Time Interrupt Set Time -35 -45 Interrupt Reset Time -35 -45 SYMBOL tAS tWR tINS MIN 0 0 ----MAX --30 35 ns 30 35 UNITS ns ns ns
tINR
TABLE 11. 7025E TRUTH TABLE FOR INTERRUPT FLAG CONTROL 1
Memory
FUNCTION Left Port Set right INTL flag Reset right INTL flag Set left INTL flag Reset left INTL flag Right Port Set right INTR flag Reset right INTR flag Set left INTR flag Reset left INTR flag 1. Assumes BUSYL = BUSYR = H. 2. If BUSYR = L, then no change. 3. If BUSYL = L, then no change.
R/W
CS
OS
A0-A12 1FFF X X 1FFE X 1FFF 1FFE X
INT
L X X X X X L X
L X X L X L L X
X X X L X L X X
X X L2 H3 L3 H2 X X
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 12. 7025E TRUTH TABLE FOR ARBITRATION OPTIONS
OPTIONS CS Busy Logic Master Busy Logic Slave Interrupt Logic Semaphore Logic L L L L L L H H UB X L X L X L X X INPUTS LB L X L X L X X X M/S H H L L X X H L SEM H H H H H H L L BUSY Output Signal Input Signal -H HI-Z OUTPUTS INT --Output Signal --
TABLE 13. 7025E NON-CONTENTION READ/WRITE CONTROL
INPUTS 1 CS H X L L L L L L X R/W X X L L L H H H X OE X X X X X L L L H UB X H L H L L H L X LB X H H L L H L L X SEM H H H H H H H H X OUTPUTS I/O8-I/O15 HI-Z HI-Z DATAIN HI-Z DATAIN DATAOUT HI-Z DATAOUT HI-Z I/O0-I/O7 HI-Z HI-Z HI-Z DATAIN DATAIN HI-Z DATAOUT DATAOUT HI-Z Deselected power down Both bytes deselected: Power down Write to upper byte only Write to lower byte only Write to both bytes Read upper byte only Read lower byte only Read both bytes Outputs disabled MODE
Memory
1. AOL - A12L = AOR-A12R.
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 14. 7025E SEMAPHORE READ/WRITE CONTROL 1
INPUTS CS H X H X L L X X R/W H H OE L L X X X X UB X H X H L X LB X H X H X L SEM L L L L L L OUTPUTS I/O8-I/O15 DATAOUT DATAOUT DATAIN DATAIN --I/O0-I/O7 DATAOUT DATAOUT DATAIN DATAIN --Read data in semaphore flag Read data in semaphore flag Write DinO into semaphore flagf Write DinO into semaphore flag Not allowed Not allowed MODE
1. AOL - A12L = AOR-A12R.
Memory
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All data sheets are subject to change without notice
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
FIGURE 1. TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE1,2,3
7025E
FIGURE 2. TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE1,4,5
Memory
1. 2. 3. 4. 5.
F/W is high for read cycles. Device is continuously enabled, CS = VIL, UB or LB = VL. This waveform cannot be used for semaphore reads. CE = VIL. Addresses valid prior to or coincident with CS transition. To access RAM, CS = VL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL.
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
FIGURE 3. TIMING WAVEFORM OF READ CYCLE NO. 3, EITHER SIDE1,3,4,5
7025E
FIGURE 4. TIMING WAVEFORM OF READ WITH BUSY 2,3,4 (FOR MASTER)
Memory
1. 2. 3. 4.
To ensure math, the earlier of the two ports wins. Write cycle parameters should be adhered to, to ensure proper writing. Device is continuously enable for both ports. OE = L for the reading port.
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
FIGURE 5. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT 1,2,3 (FOR SLAVE ONLY)
Memory
1. Assume BUSY Input = H or the writing port, and OE = L for the reading port. 2. Write cycle parameters should be adhered to, to ensure proper writing. 3. Device is continuously enable for both ports.
FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING1,2,3,7
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All data sheets are subject to change without notice
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
FIGURE 7. TIMING WAVEFORM OF WRITE CYCLE NO. 2, CS CONTROLLED TIMING 1,2,3,5
FIGURE 8. TIMING WAVEFORM OF WRITE WITH BUSY (FOR SLAVE)
Memory
1. 2. 3. 4. 5. 6. 7.
8. 9.
R/W must be high during all address transitions. A write occurs during the overlap (tSW to tWF) of a low CS or SEM and a low R/W. T.WF is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle. During this period, the I/O pins are in the output state, and input signals must not be applied. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. Transitions measured = 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sample and not 100% tested. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of two or (tWZ +tDW) to allow the I/O driver to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. To access RAM, CS = VIL, SEM = VIH. To access upper byte, CS = VIL, UB = VIL, SEM = VIH. To access lower byte, CS = VIL, LB = VIL, SEM = VIH.
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All data sheets are subject to change without notice
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
FIGURE 9. TIMING WAVEFORM OF CONTENTION CYCLE NO. 1, CS ARBITRATION (FOR MASTER)
Memory
FIGURE 10. TIMING WAVEFORM OF CONTENTION CYCLE NO. 2, ADDRESS VALID ARBITRATION (FOR MASTER
ONLY) 1
LEFT ADDRESS VALID FIRST
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
RIGHT ADDRESS VALID FIRST
7025E
1. CSL = CSR = VIL.
FIGURE 11. WAVEFORM OF INTERRUPT TIMING 1 SET ADDRESS
Memory
CLEAR ADDRESS
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A". 2. See interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first.
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All data sheets are subject to change without notice
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
FIGURE 12. 32-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
7025E
1. No arbitration in Master/Slave. BUSY - IN inhibits write in Master/Slave.
FIGURE 13. TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE 1
Memory
1. CS = VIH for the duration of the above timing (both write and read cycle).
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(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
FIGURE 14. TIMING WAVEFORM OF SEMAPHORE CONTENTION 1,3,4
7025E
1. DOR = DOL = VIL, CSR = CSL = VIH, semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. Either side "A" = left and side "B" = right, or side "A" = right and side "B" = left. 3. This parameter is measured from the point where R/WA or SEMA goes high until R/WB or SEMB goes high. 4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guaranty which side will obtain the flag.
Memory
08.15.02 Rev 2
All data sheets are subject to change without notice
17
(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
Memory
84 PIN RAD-PAK(R) FLAT PACKAGE
SYMBOL MIN A A1 b c D D1 e S1 F1 F2 F3 F4 L L1 L2 N
08.15.02 Rev 2
DIMENSION NOM 0.176 0.123 0.010 0.006 0.650 0.500 BSC 0.025 BSC 0.013 0.540 0.415 0.412 0.560 -1.595 0.940 0.070 0.545 0.420 0.415 0.565 1.620 1.600 0.950 84
All data sheets are subject to change without notice
MAX 0.189 0.133 0.014 0.010 0.665
0.163 0.113 0.006 0.004 0.635
-0.550 0.425 0.418 0.570 1.635 1.615 0.960
18
(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
Q84-01 Note: All dimensions in inches Important Notice:
7025E
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.
Memory
08.15.02 Rev 2
All data sheets are subject to change without notice
19
(c)2002 Maxwell Technologies All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
Product Ordering Options
Model Number 7025E RP Q X -XX Feature Access Time
7025E
Option Details
35 = 35 ns 45 = 45 ns
Screening Flow
Monolithic S = Maxwell Class S B = Maxwell Class B I = Industrial (testing @ -55C, +25C, +125C) E = Engineering (testing @ +25C)
Memory
Package
Q = Quad Flat Pack
Radiation Feature
RP = RAD-PAK(R) package
Base Product Nomenclature
(8K x 16-Bit) Dual Port RAM HighSpeed CMOS
08.15.02 Rev 2
All data sheets are subject to change without notice
20
(c)2002 Maxwell Technologies All rights reserved.

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